This invention relates to analog-to-digital converters (abbreviated to A/D converters or ADCs), in particular A/D converters which operate in accordance with the successive approximation (S/A) method.
Analog-to-digital converters are essential elements to many integrated circuit applications, such as automatic control, adjustment, data acquisition, and data processing systems, wherein they provide "interfaces" for converting analog entities (real-word parameters) into digital information adapted to be processed through logic circuits, memories, and microprocessors.
Analog-to-digital converters of the successive approximation type are the more widely used ones because they combine good speed of execution (200 to 500 ns per bit) with low cost, ease of fabrication (a single LST chip), and good accuracy; state-of-art embodiments of such converters being capable of handling up to 12 bits.
A/D converters of the S/A type are standard items in the lines offered by all major suppliers of semiconductors.
Examples of their construction can be found in "Data Acquisition Databook", 1993 Edition, National Semiconductor, which is hereby incorporated by reference.
The architecture of a successive approximation analog-to-digital converter usually comprises a comparator, a digital-to-analog (D/A) converter, and a control logic, as shown in FIG. 1. The control logic is often referred to as the Successive Approximation Register (SAR). The SAR is operative to determine the value of each bit in a sequential manner, according to the comparator output. The SAR starts the conversion cycle by putting the most significant bit, MSB, of the word equal to 1, and all the other bits equal to 0 (attempt). This digital word is applied to the D/A converter, which will generate an analog signal whose value is one half the conversion range Vref/2 which is being compared to the input Vin. If the comparator output is high, the control logic will set the MSB to 1, whereas if the output is low, the control logic will set the MSB to 0 (decision). At this stage, the value of the MSB has been determined. The approximation process continues with the application of a digital word to the D/A converter wherein the MSB has its proper value and the second or attempt bit is 1 and all the remaining bits are 0. Once again, the output from the D/A is compared to its input: if the comparator output is high, the second bit is set to 1, otherwise to 0, and so on to the least significant bit, LSB, of the word.
The contents of the SAR register represent the digital outcome of the completed conversion.
The SAR is a sequential finite-state machine (MSF) which generates the sequence of states shown in the following chart (wherein the case of the number of bits being N=8 has been considered, for simplicity).
The sequence evolves as follows through the chart: in step 1, the initializing configuration is enforced. Over the following steps, three actions are possible on the single bit: enforcement of the attempt 1, result of the decision from the comparator, memory of the preceding value.
______________________________________ Comparator Step: D/A input word output ______________________________________ 0 1 0 0 0 0 0 0 0 a7 1 a7 1 0 0 0 0 0 0 a6 2 a7 a6 1 0 0 0 0 0 a5 3 a7 a6 a5 1 0 0 0 0 a4 4 a7 a6 a5 a4 1 0 0 0 a3 5 a7 a6 a5 a4 a3 1 0 0 a2 6 a7 a6 a5 a4 a3 a2 1 0 a1 7 a7 a6 a5 a4 a3 a2 a1 1 a0 result a7 a6 a5 a4 a3 a2 a1 a0 -- ______________________________________
The successive approximation algorithm whereby one can describe the chart is the following. Taking any conversion step whichever, the next step value for each bit k of the input word to the D/A can have one of three values:
that of the left side bit (k+1), if all the bits (k-1, k-2, . . . , 0) which are less significant than the bit k, and the bit k itself, have "0" value; or PA1 that of the comparator output, if all the least significant bits of the word have the value of "0" and the bit k carries a value of "1" or PA1 that of the bit k, if at least one of the least significant bits carries a value of "1".
By running this algorithm over a suitable logic network, the same storage elements (flip-flops) that hold the result of the conversion can be used to encode the 2.sup.N possible states of the finite-state machine MSF. In fact, where an N-bit successive approximation A/D converter is to be provided, the skilled artisan will find that the MSF machine on which the algorithm is to be run requires at least 2.sup.N states, that is at least N flip-flops.
However, current embodiments of registers for successive approximation analog-to-digital converters employ a number of flip-flops which is at least twice as large as the minimum.
The underlying technical problem of this invention is to provide a no-redundancy register for successive approximation analog-to-digital converters.
This problem is solved by a shift register of the type indicated above and as defined in the claims appended to this specification.
The features and advantages of a shift register according to the invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.